1. Field of the Invention
The present invention relates to a test system, and in particular relates to a test system capable of simultaneously testing several devices under test.
2. Description of the Prior Art
To ensure the quality of each electronic device for sales, a test is performed to determine whether the electronic device, such as an integrated circuit, a wafer or a chip, meets qualification standards.
FIG. 1 is a schematic diagram of testing a single device. Here, the device is a chip. A tester 10 sends a control command via a general purpose interface bus (GPIB) 12 to control a measuring instrument 14, and measures a chip under test 16 via the measuring instrument 14. The test result TR generated by the chip under test 16 is sent to the tester 10 for data analysis, and finally the tester 10 determines if the chip under test 16 passes the test. With this method, the tester 10 can only test a single chip under test 16 at a time, hindering mass production efficiency.
FIG. 2 is a schematic diagram of testing several devices. Here, the devices are chips. A tester 20 sends a control command via a GPIB 22 to control measuring instruments 241-243, and switches relays 261-263 via the measuring instruments 241-243 to measure the corresponding chips tinder test 281-283, and then the test results TR1-TR3 of the chips under test 281-283 are sent to the tester 20 for data analysis. However, since the command address of the tester 20 supports only one measuring instrument at a time, it is necessary to use the relays 261-263 to control the measuring process, thus hindering the time it takes to test several chips under test 281-283 in one working period due to the chip testing serial structure.
For the chip testing methods mentioned above, much time is required when testing a multitude of chips under test. Thus, a novel test system which raises chip testing efficiency for testing several chips simultaneously, without drastically increasing costs is desired.